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LXT386
QUAD T1/E1/J1 Transceiver
Datasheet
The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers and four independent transmitters in a single PBGA-160 or LQFP-100 package. The transmit drivers provide low impedance independent of the transmit pattern and supply voltage variations.The LXT386 transmits shaped waveforms meeting G.703 and T1.102 specifications. The LXT386 exceeds the latest transmit return loss specifications, such as ETSI ETS-300166. The LXT386's differential receiver architecture provides high noise interference margin and is able to work with up to 12 dB of cable attenuation. The digital clock recovery PLL and jitter attenuator are referenced to a low frequency 1.544 MHz or 2.048 MHz clock. The LXT386 incorporates an advanced crystal-less jitter attenuator switchable between the receive and transmit path. The jitter attenuation performance meets the latest international specifications such as CTR12/13. The jitter attenuation performance was optimized for Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/SDH) applications. The LXT386 can be configured as a 3 channel transceiver with G.772 compliant non intrusive protected monitoring points. It uses a single 3.3V supply for low power consumption. The constant delay characteristic of the LXT386 JA as well as a power down mode of all transmitters allows the implementation of Hitless Protection Switching (HPS) applications without the use of relays.
Applications
s s s
SONET/SDH tributary interfaces Digital cross connects Public/private switching trunk line interfaces
s s
Microwave transmission systems M13, E1-E3 MUX
As of January 15, 2001, this document replaces the Level One document LXT386 -- QUAD T1/E1/J1 Transceiver Font>.
Order Number: 249253-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT386 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Contents
1.0 2.0 3.0 Features ......................................................................................................................... 7 Pin Assignments and Signal Description ........................................................ 9 Functional Description...........................................................................................22
3.1 3.2 Initialization..........................................................................................................22 3.1.1 Reset Operation .....................................................................................22 Receiver ..............................................................................................................23 3.2.1 Loss of Signal Detector ..........................................................................24 3.2.1.1 E1 Mode ....................................................................................24 3.2.1.2 T1 Mode ....................................................................................24 3.2.1.3 Data Recovery Mode.................................................................24 3.2.2 Alarm Indication Signal (AIS) Detection .................................................24 3.2.2.1 E1 Mode ....................................................................................25 3.2.2.2 T1 Mode ....................................................................................25 3.2.3 In Service Code Violation Monitoring .....................................................25 Transmitter ..........................................................................................................25 3.3.1 Transmit Pulse Shaping .........................................................................26 3.3.1.1 Hardware Mode .........................................................................26 3.3.1.2 Host Mode .................................................................................26 3.3.2 Transmit Pulse Shaping .........................................................................27 3.3.2.1 Output Driver Power Supply ......................................................27 3.3.2.2 Power Sequencing ....................................................................27 Driver Failure Monitor..........................................................................................27 Line Protection ....................................................................................................28 Jitter Attenuation .................................................................................................30 Loopbacks ...........................................................................................................31 3.7.1 Analog Loopback....................................................................................31 3.7.2 Digital Loopback.....................................................................................32 3.7.3 Remote Loopback ..................................................................................32 3.7.4 Transmit All Ones (TAOS)......................................................................32 G.772 Performance Monitoring ...........................................................................33 Hitless Protection Switching (HPS) .....................................................................34 Operation Mode Summary ..................................................................................34 Interfacing with 5V logic ......................................................................................35 Parallel Host Interface .........................................................................................35 3.12.1 Motorola Interface ..................................................................................35 3.12.2 Intel Interface..........................................................................................36 Interrupt Handling................................................................................................36 3.13.1 Interrupt Enable......................................................................................36 3.13.2 Interrupt Clear ........................................................................................37 Serial Host Mode.................................................................................................37
3.3
3.4 3.5 3.6 3.7
3.8 3.9 3.10 3.11 3.12
3.13
3.14
4.0 5.0
Register Descriptions.............................................................................................38 JTAG Boundary Scan.............................................................................................45
5.1 5.2 Overview .............................................................................................................45 Architecture .........................................................................................................45
Datasheet
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LXT386 -- QUAD T1/E1/J1 Transceiver
5.3 5.4 5.5
TAP Controller..................................................................................................... 45 JTAG Register Description.................................................................................. 47 5.4.1 Boundary Scan Register (BSR).............................................................. 48 Device Identification Register (IDR) .................................................................... 50 5.5.1 Bypass Register (BYR) .......................................................................... 50 5.5.2 Analog Port Scan Register (ASR) .......................................................... 50 5.5.3 Instruction Register (IR) ......................................................................... 51 Recommendations and Specifications ................................................................ 75
6.0 7.0
Test Specifications.................................................................................................. 53
6.1
Mechanical Specifications ................................................................................... 76
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 LXT386 Block Diagram ......................................................................................... 7 LXT386 Detailed Block Diagram ........................................................................... 8 LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Package Markings......................................................................................................... 9 LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments........................... 10 Pullup Resistor to RESET ................................................................................... 23 50% AMI Encoding.............................................................................................. 26 External Transmit/Receive Line Circuitry ............................................................ 29 Jitter Attenuator Loop.......................................................................................... 31 Analog Loopback ................................................................................................ 31 Digital Loopback.................................................................................................. 32 Remote Loopback ............................................................................................... 32 TAOS Data Path ................................................................................................. 33 TAOS with Analog Loopback .............................................................................. 33 Serial Host Mode Timing..................................................................................... 37 LXT386 JTAG Architecture ................................................................................. 45 JTAG State Diagram ........................................................................................... 47 Analog Test Port Application............................................................................... 52 Transmit Clock Timing Diagram.......................................................................... 59 Receive Clock Timing Diagram........................................................................... 60 JTAG Timing ....................................................................................................... 61 Non-Multiplexed Intel Mode Read Timing ........................................................... 62 Multiplexed Intel Read Timing............................................................................. 63 Non-Multiplexed Intel Mode Write Timing ........................................................... 64 Multiplexed Intel Mode Write Timing ................................................................... 65 Non-Multiplexed Motorola Mode Read Timing.................................................... 66 Multiplexed Motorola Mode Read Timing............................................................ 67 Non-Multiplexed Motorola Mode Write Timing .................................................... 68 Multiplexed Motorola Mode Write Timin.............................................................. 69 Serial Input Timing .............................................................................................. 70 Serial Output Timing ........................................................................................... 70 E1, G.703 Mask Templates................................................................................. 71 T1, T1.102 Mask Templates ............................................................................... 72 LXT386 Jitter Tolerance Performance ................................................................ 73 Jitter Transfer Performance ................................................................................ 74
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
35 36 37
Output Jitter for CTR12/13 applications ..............................................................75 60 Plastic Ball Grid Array (PBGA) Package Dimensions ....................................76 100 Pin Low Quad Flat Packages (LQFP) Dimensions ......................................77
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Assignments and Signal Descriptions...........................................................11 Line Length Equalizer Inputs...............................................................................27 Jitter Attenuation Specifications ..........................................................................30 Operation Mode Summary ..................................................................................34 Microprocessor Parallel Interface Selection ........................................................35 Serial and Parallel Port Register Addresses .......................................................38 Register Bit Names .............................................................................................38 ID Register, ID (00H)...........................................................................................39 Analog Loopback Register, ALOOP (01H)..........................................................39 Remote Loopback Register, RLOOP (02H) ........................................................40 TAOS Enable Register, TAOS (03H) ..................................................................40 LOS Status Monitor Register, LOS (04H) ...........................................................40 DFM Status Monitor Register, DFM (05H) ..........................................................40 LOS Interrupt Enable Register, LIE (06H)...........................................................40 DFM Interrupt Enable Register, DIE (07H)..........................................................40 LOS Interrupt Status Register, LIS (08H)............................................................41 DFM Interrupt Status Register, DIS (09H)...........................................................41 Software Reset Register, RES (0AH)..................................................................41 Performance Monitoring Register, MON (0BH)...................................................41 Digital Loopback Register, DL (0CH) ..................................................................41 LOS/AIS Criteria Register, LCS (0DH)................................................................41 Automatic TAOS Select Register, ATS (0EH).....................................................42 Global Control Register, GCR (0FH)...................................................................42 Pulse Shaping Indirect Address Register, PSIAD (10H) .....................................43 Pulse Shaping Data Register, PSDAT (11H) ......................................................43 Output Enable Register, OER (12H) ...................................................................43 AIS Status Monitor Register, AIS (13H) ..............................................................43 AIS Interrupt Enable Register, AISIE (14H) ........................................................44 AIS Interrupt Status Register, AISIS (15H) .........................................................44 TAP State Description .........................................................................................46 Device Identification Register (IDR) ....................................................................50 Analog Port Scan Register (ASR) .......................................................................51 Instruction Register (IR) ......................................................................................51 Absolute Maximum Ratings.................................................................................53 Recommended Operating Conditions .................................................................53 DC Characteristics ..............................................................................................54 E1 Transmit Transmission Characteristics..........................................................55 E1 Receive Transmission Characteristics...........................................................55 T1 Transmit Transmission Characteristics ..........................................................56 T1 Receive Transmission Characteristics ...........................................................57 Jitter Attenuator Characteristics ..........................................................................58 Analog Test Port Characteristics.........................................................................59 Transmit Timing Characteristics..........................................................................59 Receive Timing Characteristics...........................................................................60
Datasheet
5
LXT386 -- QUAD T1/E1/J1 Transceiver
45 46 47 48 49 50 51 52 53
JTAG Timing Characteristics .............................................................................. 61 Intel Mode Read Timing Characteristics ............................................................. 61 Intel Mode Write Timing Characteristics ............................................................. 63 Motorola Bus Read Timing Characteristics......................................................... 65 Motorola Mode Write Timing Characteristics ...................................................... 67 Serial I/O Timing Characteristics......................................................................... 69 Transformer Specifications3 ............................................................................... 70 G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 71 T1.102 1.544 Mbit/s Pulse Mask Specifications.................................................. 71
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
1.0
Features
* Single rail 3.3V supply with 5V tolerant inputs * Low power consumption of 150mW per channel (typical) * Superior crystal-less jitter attenuator
-- Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications -- Optimized for SONET/SDH applications, meets ITU G.783 mapping jitter specification -- Constant throughput delay jitter attenuator
* * * * * * * * *
Hitless Protection Switching (HPS) for 1 to 1 protection without relays HDB3, B8ZS, or AMI line encoder/decoder Provides protected monitoring points per ITU G.772 Analog/digital and remote loopback testing functions LOS per ITU G.775, ETS 300 233 and T1.231 8 bit parallel or 4 wire serial control interface Hardware and Software control modes JTAG Boundary Scan test port per IEEE 1149.1 160 PBGA and 100 pin LQFP packages
Figure 1. LXT386 Block Diagram
JTAG SERIAL/ PARALLEL PORT
MODE HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) LOOP 0..3 JASEL CLKE MCLK
LOS DATA SLICER RTIP ANALOG LOOPBACK DIGITAL LOOPBACK DATA CLOCK CLOCK RECOVERY JITTER ATTENUATOR RX OR TX PATH
LOS
RPOS REMOTE LOOPBACK B8ZS / HDB3 DECODER RCLK RNEG
RRING
G.772 MONITOR
LINE DRIVER PULSE PULSE SHAPER
TTIP
TRING
JITTER ATTENUATOR RX OR TX PATH
TPOS B8ZS / HDB3 ENCODER TCLK TNEG
0 1 2 3
Datasheet
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LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 2. LXT386 Detailed Block Diagram
JTAG SERIAL/ PARALLEL PORT
HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE)
MODE LOOP 0..7 JASEL CLKE MCLK LOS3
Transceiver 3
LOS DATA SLICER ANALOG LOOPBACK DATA CLOCK CLOCK RECOVERY JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK DIGITAL LOOPBACK
RTIP3 RRING3 TTIP3 TRING3
G.772 Protected Monitoring Point
B8ZS / HDB3 DECODER
RPOS3 RCLK3 RNEG3 TPOS3 TCLK3 TNEG3
LINE DRIVER PULSE PULSE SHAPER
JITTER ATTENUATOR RX OR TX PATH
B8ZS / HDB3 ENCODER
RTIP2/RRING2 TTIP2/TRING2
Transceiver 2
LOS2 RPOS2/RNEG2/RCLK2 TPOS2/TNEG2/TCLK2
RTIP1/RRING1 TTIP1/TRING1
Transceiver 1
LOS1 RPOS1/RNEG1/RCLK1 TPOS1/TNEG1/TCLK1
Transceiver 0
LOS DATA SLICER ANALOG LOOPBACK JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK DIGITAL LOOPBACK
LOS0 RPOS0 RCLK0 RNEG0 TPOS0 TCLK0 TNEG0
RTIP0 RRING0 TTIP0 TRING0 A3 - A0
MUX
DATA CLOCK CLOCK RECOVERY
B8ZS / HDB3 DECODER
LINE DRIVER PULSE PULSE SHAPER
JITTER ATTENUATOR RX OR TX PATH
B8ZS / HDB3 ENCODER
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
2.0
Pin Assignments and Signal Description
Figure 3. LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Package Markings
RESET
MODE MCLK 78
CLKE
MUX
ALE ACK INT
AT1
100 99
98
97 96 95
94 93
92
91
90 89
88
87 86 85 84
83
82 81
80 79
77 76
AT2
OE
CS
D7 D6 D5
D4 D3
D2
D1 D0
A4
A3 A2
A1 A0
MOT R/W DS VCC GND VCC GND VCC VCC GND GND TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 LOS1 TCLK0 TPOS0 TNEG0 RCLK0 RPOS0 RNEG0 LOS0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67
VCC GND TDO TRST TMS TDI TCK VCC VCC GND GND TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 LOS2 TCLK3 TPOS3 TNEG3 RCLK3 RPOS3 RNEG3 LOS3
Part # LOT # FPO #
LXT386LE XX XXXXXX XXXXXXXX
Rev #
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TGND0 RTIP0 RRING0
TVCC1 RRING1
RRING2
TVCC3 RRING3
TGND1 TRING1
TRING2 TGND2
RTIP2
TGND3 TRING3 TTIP3
TVCC0
RTIP1
TVCC2 TTIP2
TRING0
Package Topside Markings Marking Part # Rev # Lot # FPO # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Definition
Datasheet
RTIP3
TTIP0
TTIP1
N/C
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LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 4. LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments
14 A B C D E F G H J K L M N P
N/C
13
N/C
12
N/C
11
TVCC
10
N/C
9
GND
8
N/C
7
N/C
6
GND
5
N/C
4
VCC
3
N/C
2
N/C
1
N/C
A B C D E F G H J K L M N P
GND
GND
GND
TVCC
N/C
GND
N/C
N/C
GND
N/C
VCC
GND
GND
GND
N/C
N/C
N/C
VCC
N/C
GND
N/C
N/C
GND
N/C
VCC
N/C
N/C
N/C
GND
GND
GND
VCC
N/C
GND
N/C
N/C
GND
N/C
VCC
GND
GND
GND
OE
CLKE
N/C
N/C
N/C
N/C
MODE
MCLK
TCK
TDO
TDI
TMS
A 4
A 3 A 0
A 2
A 1
VCC
AT 2 AT 1
TRST
GND
GND
D0
VCC
LXT386BE
MOT GND
VCC
(BOTTOM VIEW)
GND
D1
D2
VCC
DS
R/W
ALE
CS
D3
D4
D5
D6
ACK
INT
LOS 2 TNEG 2 RNEG 2
LOS 3 TVCC 2 TVCC 2 TTIP 2 TRING 2 TGND 2 TGND 2
RRING RRING
LOS 0 TGND 1 TGND 1 TTIP 1 TRING 1 TVCC 1 TVCC 1
LOS 1 TNEG 1 RNEG 1
MUX
D7
TCLK 2 RCLK 2
TPOS 2 RPOS 2
2 RTIP 2
1 RTIP 1
TPOS 1 RPOS 1
TCLK 1 RCLK 1
TCLK 3 RCLK 3
TPOS 3 RPOS 3
TNEG 3 RNEG 3
TVCC 3 TVCC 3
TTIP 3 TRING 3
TGND 3 TGND 3
RRING
RRING
3 RTIP 3
0 RTIP 0
TGND 0 TGND 0
TTIP 0 TRING 0
TVCC 0 TVCC 0
TNEG 0 RNEG 0
TPOS 0 RPOS 0
TCLK 0 RCLK 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions
Pin # LQFP Symbol I/O1 Description Master Clock. MCLK is an independent, free-running reference clock. It's frequency should be 1.544 MHz for T1 operation and 2.048 MHz for E1 operation. This reference clock is used to generate several internal reference signals: * Timing reference for the integrated clock recovery unit * Timing reference for the integrated digital jitter attenuator * Generation of RCLK signal during a loss of signal condition * Reference clock during a blue alarm transmit all ones condition * Reference timing for the parallel processor wait state generation logic If MCLK is High, the PLL clock recovery circuit is disabled. In this mode, the LXT386 operates as simple data receiver. If MCLK is Low, the complete receive path is powered down and the output pins RCLK, RPOS and RNEG are switched to Tri-state mode. MCLK is not required if LXT386 is used as a simple analog front-end without clock recovery and jitter attenuation. Note that wait state generation via RDY/ACK is not available if MCLK is not provided. Mode Select. This pin is used to select the operating mode of the LXT386. In Hardware Mode, the parallel processor interface is disabled and hardwired pins are used to control configuration and report status. In Parallel Host Mode, the parallel port interface pins are used to control configuration and report status. In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are used.
E1
78
MCLK
DI
E2
79
MODE
DI
MODE L H Vcc/2
Operating Mode Hardware Mode Parallel Host Mode Serial Host Mode
For Serial Host Mode, the pin should connected to a resistive divider consisting of two 10 k resistors across VCC and Ground. F4 89 A4 DI Address Select. In host mode, this pin is Address 4 input pin. In hardware mode this pin must be connected to Ground.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
11
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description Protected Monitoring/Address Select Inputs. Hardware Mode In hardware mode these pins are used to select a specific port for non intrusive monitoring. During protection monitoring receiver 0 inputs are internally connected to a specific transmit or receive port. Receiver 0 routes the data from the selected port to its data and clock recovery circuits. The data on the monitor port can be routed to TTIP0/TRING0 by activating the remote loopback for channel 0 (TCLK0 must be active in order for this operation to take place). In addition, the recovered clock and data can be observed at the RCLK0/RPOS0/RNEG0 outputs. If A0-A3 are Low, the LXT386 is configured as a quad line transceiver without monitoring capability. A3 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selection No Protection Monitoring Receiver 1 Receiver 2 Receiver 3 Reserved Reserved Reserved Reserved No Protection Monitoring Transmitter 1 Transmitter 2 Transmitter 3 Reserved Reserved Reserved Reserved
F3 F2 F1 G3
88 87 86 85
A3 A2 A1 A0
DI DI DI DI
0 0 0 0 0 1 1 1 1 1 1 1 1
Transmitter monitoring is not supported when the respective channel is set to analog loopback mode. Host Mode In non-multiplexed host mode, these pins function as non-multiplexed address pins. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description Loopback Mode Select/Parallel Data bus. Host Mode: When a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data port. When a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs A0 -A7. In serial Mode, D0-7 should be grounded. Hardware Mode: In hardware mode, the LXT386 works in normal operation if this pin is left open (unconnected). The LXT386 enters remote loopback mode if LOOP is Low. In this mode, data on TPOS and TNEG is ignored and data received on RTIP and RRING is looped around and retransmitted on TTIP and TRING. Note: in data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. The LXT386 enters analog local loopback mode if LOOP=1 and DLOOP=0. In this mode, data received on RTIP and RRING is ignored and data transmitted on TTIP and TRING is internally looped around and routed back to the receive inputs. The LXT386 enters digital local loopback if LOOP=1 and DLOOP=1. In this mode, data received on TCLK/TPOS/TNEG is digitally looped back to RCLK/RPOS/RNEG. LOOP Open 0 1 1 DLOOP x x 0 1 Operating Mode Normal Mode Remote Loopback Analog Local Loopback Digital Local Loopback
G2 H3 H2 J4 J3 J2 J1 K1
90 91 92 93 94 95 96 97
D0/LOOP0 D1/LOOP1 D2/LOOP2 D3/LOOP3 D4/DLOOP0 D5/DLOOP1 D6/DLOOP2 D7/DLOOP3
DI/O DI/O DI/O DI/O DI/O DI/O DI/O DI/O
Note: Note: when these inputs are left open, they stay in a high impedance state. Therefore, the layout design should not route signals with fast transitions near the LOOP pins. This practice will minimize capacitive coupling. L1 L2 L3 M1 M2 M3 K3 12 13 14 15 16 17 18 TCLK1 TPOS1/ TDATA1 TNEG1/ UBS1 RCLK1 RPOS1/ RDATA1 RNEG1/ BPV1 LOS1 DI DI DI DI DI DO DO DO DO DO DO Transmit Clock. Transmit Positive Data. Transmit Data. Transmit Negative Data. Unipolar/Bipolar Select. Receive Clock. Receive Positive Data. Receive Data. Receive Negative Data. Bipolar Violation Detect. Loss of Signal.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
13
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description Transmit Clock. During normal operation TCLK is active, and TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is Low, the output drivers enter a low power high Z mode. If TCLK is High for more than 16 clock cycles the pulse shaping circuit is disabled and the transmit output pulse widths are determined by the TPOS and TNEG duty cycles. When pulse shaping is disabled, it is possible to overheat and damage the LXT384 device by leaving transmit inputs high continuously. For example a programmable ASIC might leave all outputs high until it is programmed. To prevent this, clock one of these signals: TPOS, TNEG, TCLK or MCLK. Another solution is to set one of these signals low: TPOS, TNEG, TCLK, or OE.
N1
19
TCLK0
DI
TCLK Clocked H H L
Operating Mode Normal operation TAOS (if MCLK supplied) Disable transmit pulse shaping (when MCLK is not available) Driver outputs enter tri-state
Note that the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. Transmit Positive Data. Transmit Data. Transmit Negative Data. Unipolar/Bipolar Select. N2 20 TPOS0/ TDATA0 DI DI Bipolar Mode: TPOS/TNEG are active high NRZ inputs. TPOS indicates the transmission of a positive pulse whereas TNEG indicates the transmission of a negative pulse. TPOS 0 1 0 1 N3 21 TNEG0/ UBS0 DI DI Unipolar Mode: When TNEG/UBS is pulled High for more than 16 consecutive TCLK clock cycles, unipolar I/O is selected. In unipolar mode, B8ZS/HDB3 or AMI encoding/decoding is determined by the CODEN pin (hardware mode) or by the CODEN bit in the GCR register (software mode). TDATA is the data input in unipolar I/O mode. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected" TNEG 0 0 1 1 Space Positive Mark Negative Mark Space Selection
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Receive Clock. Normal Mode: This pin provides the recovered clock from the signal received at RTIP and RRING. Under LOS conditions there is a transition from RCLK signal (derived from the recovered data) to MCLK signal at the RCLK output. Data Recovery Mode: If MCLK is High, the clock recovery circuit is disabled and RPOS and RNEG are internally connected to an EXOR that is fed to the RCLK output for external clock recovery applications. RCLK will be in high impedance state if the MCLK pin is Low. Receive Positive. Receive Data. Receive Negative Data. Bipolar Violation Detect. Bipolar Mode: RPOS0/ RDATA0 DO DO In clock recovery mode these pins act as active high bipolar non return to zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING. A High signal on RNEG corresponds to receipt of a negative pulse on RTIP/RRING. These signals are valid on the falling or rising edges of RCLK depending on the CLKE input. In Data recovery Mode these pins act as RZ data receiver outputs. The output polarity is selectable with CLKE (Active High output polarity when CLKE is High and Active Low Polarity when CLKE is Low). RPOS and RNEG will go to the high impedance state when the MCLK pin is Low. Unipolar Mode: In uni-polar mode, the LXT386 asserts BPV High if any in-service Line Code Violation is detected. RDATA acts as the receive data output. Hardware Mode: During a LOS condition, RPOS and RNEG will remain active. Host Mode: RPOS and RNEG will either remain active or insert AIS into the receive path. Selection is determined by the RAISEN bit in the GCR register. Loss of Signal. LOS goes High to indicate a loss of signal, i.e. when the incoming signal has no transitions for a specified time interval. The LOS condition is cleared and the output pin returns to Low when the incoming signal has sufficient number of transitions in a specified time interval. See "Loss of Signal Detector" on page 24. Multiplexed/Non-Multiplexed Select. When Low the parallel host interface operates in non-multiplexed mode. When High the parallel host interface operates in multiplexed mode. In hardware mode tie this unused input low. Transmit Driver Power Supply. Power supply pin for the port 0 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. Description
P1
22
RCLK0
DO
P2
23
P3
24
RNEG0/ BPV0
DO DO
K4
25
LOS0
DO
K2
99
MUX
DI
N4, P4
26
TVCC0
S
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
15
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Transmit Tip. Transmit Ring. Description
N5 P5
27 28
TTIP0 TRING0
AO AO
These pins are differential line driver outputs. TTIP and TRING will be in high impedance state if the TCLK pin is Low or the OE pin is Low. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a `1' to the OEx bit in the Output Enable Register (OER). Transmit Driver Ground. Ground pin for the output driver. Receive Tip. Receive Ring. These pins are the inputs to the differential line receiver. Data and clock are recovered and output on the RPOS/RNEG and RCLK pins. Transmit Driver Ground. Transmit Ring. Transmit Tip. Transmit Driver Power Supply. Power supply pin for the port 1 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. Receive Ring. Receive Tip. Transmit Driver Power Supply. Power supply pin for the port 2 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. Transmit Tip. Transmit Ring. Transmit Driver Ground. Receive TIP. Receive Ring. Transmit Driver Ground. Transmit Ring. Transmit Tip. Transmit Driver Power Supply. Power supply pin for the port 3 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. Receive Ring. Receive Tip. Loss of Signal. Receive Negative Data. Bipolar Violation Detect. Receive Positive Data. Receive Data. Receive Clock.
N6, P6 P7 N7 L6, M6 M5 L5 L4, M4 L7 M7 L11, M11 L10 M10 L9, M9 M8 L8 N9, P9 P10 N10 N11, P11 N8 P8 K11 P12 P13 P14
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54
TGND0 RTIP0 RRING0 TGND1 TRING1 TTIP1 TVCC1 RRING1 RTIP1 TVCC2 TTIP2 TRING2 TGND2 RTIP2 RRING2 TGND3 TRING3 TTIP3 TVCC3 RRING3 RTIP3 LOS3 RNEG3/ BPV3 RPOS3/ RDATA3 RCLK3
S AI AI S AO AO S AI AI S AO AO S AI AI S AO AO S AI AI DO DO DO DO DO DO
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
16
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA N12 N13 N14 K12 M12 M13 M14 L12 L13 L14
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP 55 56 57 58 59 60 61 62 63 64 Symbol TNEG3/ UBS3 TPOS3/ TDATA3 TCLK3 LOS2 RNEG2/ BPV2 RPOS2/ RDATA2 RCLK2 TNEG2/ UBS2 TPOS2/ TDATA2 TCLK2 I/O1 DI DI DI DI DI DO DO DO DO DO DO DI DI DI DI DI Transmit Negative Data. Unipolar/Bipolar Select. Transmit Positive Data. Transmit Data. Transmit Clock. Loss of Signal. Receive Negative Data. Bipolar Violation Detect. Receive Positive Data. Receive Data. Receive Clock. Transmit Negative Data. Unipolar/Bipolar Select. Transmit Positive Data. Transmit Data. Transmit Clock. Interrupt. This active Low, maskable, open drain output requires an external 10k pull up resistor. If the corresponding interrupt enable bit is enabled, INT goes Low to flag the host when the LXT386 changes state (see details in the interrupt handling section). The microprocessor INT input should be set to level triggering. Data Transfer acknowledge (Motorola Mode). Ready (Intel mode). Serial Data Output (Serial Mode). Motorola Mode A Low signal during a databus read operation indicates that the information is valid. A Low signal during a write operation acknowledges that a data transfer into the addressed register has been accepted (acknowledge signal).Wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. read modify write). Intel Mode A High signal acknowledges that a register access operation has been completed (Ready Signal). A Low signal on this pin signals that a data transfer operation is in progress. The pin goes tristate after completion of a bus cycle. Serial Mode If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low, SDO is valid on the falling edge of SCLK. This pin goes into high Z state during a serial port write access. Description
K13
80
INT
DO
ACK/ K14 81 RDY/ SDO
DO DO DO
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
17
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Data Strobe (Motorola Mode). Write Enable (Intel mode). Serial Data Input (Serial Mode). DS/ DI DI DI DI Line Length Equalizer (Hardware Mode). Host Mode This pin acts as data strobe in Motorola mode and as Write Enable in Intel mode. In serial mode this pin is used as Serial Data Input. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. Read/Write (Motorola Mode). Read Enable (Intel mode). Line Length Equalizer (Hardware Mode). R / W/ DI DI DI Host Mode This pin functions as the read/write signal in Motorola mode and as the Read Enable in Intel mode. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. Address Latch Enable (Host Mode). Shift Clock (Serial Mode). Address Strobe (Motorola Mode). Line Length Equalizer (Hardware Mode). ALE/ DI DI DI DI Host Mode The address on the multiplexed address/data bus is clocked into the device with the falling edge of ALE. In serial Host mode this pin acts as serial shift clock. In Motorola mode this pin acts a an active Low address strobe. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. Description
J14
3
WR/ SDI/ LEN0
J13
2
RD/ LEN1
J12
82
SCLK/ AS/ LEN2
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
18
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description Chip Select/Jitter Attenuator Select. Host Mode This active Low input is used to access the serial/parallel interface. For each read or write operation, CS must transition from High to Low, and remain Low. Hardware Mode This input determines the Jitter Attenuator position in the data path: JASEL L H Z Transmit path Receive path Disabled JA Position
J11
98
CS/ JASEL
DI DI
Motorola/Intel/Codec Enable Select. Host Mode: When Low, the host interface is configured for Motorola microcontrollers. When High, the host interface is configured for Intel microcontrollers. H12 1 MOT/INTL/ CODEN DI DI Hardware Mode:
This pin determines the line encode/decode selection when in unipolar mode:
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively. When High, enables AMI encoder/decoder (transparent mode).
G13 H13 G12
76 77 72
AT2 AT1 TRST
AO AI
JTAG Analog Output Test Port 2. JTAG Analog Input Test Port 1. JTAG Controller Reset. Input is used to reset the JTAG controller. TRST is pulled up internally and may be left disconnected.
F11 F14 F13
71 69 73
TMS TCK TDO
DI DI DO
JTAG Test Mode Select. Used to control the test logic state machine. Sampled on rising edge of TCK. TMS is pulled up internally and may be left disconnected. JTAG Clock. Clock input for JTAG. Connect to GND when not used. JTAG Data Output. Test Data Output for JTAG. Used for reading all serial configuration and test data from internal test logic. Updated on falling edge of TCK. JTAG Data Input. Test Data input for JTAG. Used for loading serial instructions and data into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may be left disconnected. Output Driver Enable. If this pin is asserted Low all analog driver outputs immediately enter a high impedance mode to support redundancy applications without external mechanical relays. All other internal circuitry stays active. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a `1' to the OEx bit in the Output Enable Register (OER).
F12
70
TDI
DI
E14
83
OE
DI
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
19
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 1.
Ball # PBGA
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description Clock Edge Select. In clock recovery mode, setting CLKE High causes RDATA or RPOS and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK. Setting CLKE Low makes RDATA or RPOS and RNEG to be valid on the rising edge of RCLK and SDO to be valid on the falling edge of SCLK. In Data recovery Mode, RDATA or RPOS/RNEG are active High output polarity when CLKE is High and active low polarity when CLKE is Low.
E13
84
CLKE
DI
CLKE Low High
RPOS/RNEG
RCLK RCLK SCLK SCLK
SDO
N/C2
100
RESET
DI
Reset Input. (Added in Revision B1) In either hardware mode or software mode, setting RESET low will begin to initialize the LXT386 and freeze the device until set high. One microsecond after setting RESET high, initialization will complete and the LXT386 will be ready for normal operation. For Revision B1 only, the device requires a pull up resistor to VCC at this pin between 1 and 10 kohms in value. It is not necessary to retain the pull up resistor for any other revision. Please refer to the section on Reset Operation for more information. The BGA package does not have this pin feature.
A6, A9 B: 1, 2, 3, 6, 9, 12, 13, 14 C6, C9 D: 1, 2, 3, 6, 9, 12, 13, 14 G4, G11 H4, H11 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected" 5, 7, 10, 11, 65, 66, 74 GND S Power Supply Ground. Connect all pins to power supply ground.
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 1.
Ball # PBGA A4, B4, C4, C11, D4, D11, G1, G14, H1, H14 A11, B11 A: 1, 2, 3, 5, 7, 10, 12, 13, 14 B: 7, 8, 10 C: 1, 2, 3, 5, 7, 8, 10, 12, 13, 14 D: 5, 7, 8, 10 E: 3, 4, 11, 12
Pin Assignments and Signal Descriptions (Continued)
Pin # LQFP Symbol I/O1 Description
4, 6, 8, 9, 67, 68, 75,
VCC
S
Power Supply. Connect all pins to +3.3 volt power supply.
-
TVCC
S
Transmit Driver Power Supply. Power supply pins for the output drivers. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to "Transmitter" on page 25 for details.
50
N/C
NC
Not Connected. These pins must be left open for normal operation.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means "Not Connected"
Datasheet
21
LXT386 -- QUAD T1/E1/J1 Transceiver
3.0
Functional Description
Figure 1 is a simplified block diagram of the LXT386. The LXT386 is a fully integrated quad line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. These two lines comprise a digital data loop for full duplex transmission. The LXT386 can be controlled through hard-wired pins or by a microprocessor through a serial or parallel interface (Host mode). The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT386 is designed to operate without any reference clock when used as an analog front-end (line driver and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All four clock recovery circuits share the same reference clock defined by the MCLK input signal.
3.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 60% of VCC. During power-up, an internal reset sets all registers to their default values and resets the status and state machines for the LOS.
3.1.1
Reset Operation
In Revision B1, no connect pin 100 was converted to the RESET pin. Only revision B1 requires a pull up resistor to VCC at pin 100, the pull up resistor is unnecessary for all other revisions. Figure 4 shows the connections needed for revision B1 only. Note: The BGA package does not have a RESET pin. There are two methods of resetting the LXT386: 1. Override Reset - Setting the RESET pin low in either hardware mode or host mode. Until the RESET pin returns high, the LXT386 remains frozen and will not function. Once the RESET pin has returned high, the LXT386 will operaate normally. Override Reset changes all the internal registers to their default values. 2. Software Reset - Writing to the RES reset register initiates a 1microsecond reset cycle, except in Intel non-multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please refer to Host mode section for more information. This operation changes all LXT386 registers to their default values.
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 5. Pullup Resistor to RESET
VCC
1K
100
RESET
LXT386LE
3.2
Receiver
The four receivers in the LXT386 are identical. The following paragraphs describe the operation of one. The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG validation relative to RCLK is pin selectable (CLKE). The receive signal is processed through the peak detector and data slicers. The peak detector samples the received signal and determines its maximum value. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1 applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the peak value. This threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the threshold is 50% (typical). The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from impulsive noise. After processing through the data slicers, the received signal goes to the data and timing recovery section. The data and timing recovery circuits provide an input jitter tolerance better than required by Pub 62411 and ITU G.823, as shown in Test Specifications, Figure 33. Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data.
Datasheet
23
LXT386 -- QUAD T1/E1/J1 Transceiver
3.2.1
Loss of Signal Detector
The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal detection circuit. It is independent of its internal data slicer comparators and complies to the latest ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be configured to comply to the ETSI ETS 300 233 specification (LACS Register). In hardware mode, the LXT386 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation. The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is required for receive operation. When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the data content at the receiver input during the entire LOS detection period for that channel.
3.2.1.1
E1 Mode
In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32 consecutive pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit period) with no more than 15 consecutive zeros and the signal level exceeds 250mV (typical), the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048 consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when the incoming signal has transitions when the signal level is equal or greater than 250mV for more than 32 consecutive pulse intervals. This mode is activated by setting the LACS register bit to one. If it is necessary to use AIS with LOS, see errata 10.3 for a way to implement this.
3.2.1.2
T1 Mode
The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for 175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a pulse. The incoming signal is considered to have transitions when the signal level is equal or greater than 250mV.
3.2.1.3
Data Recovery Mode
In data recovery mode the LOS digital timing is derived from a internal self timed circuit. RPOS/ RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775 recommendation. The LXT386 monitors the incoming signal amplitude. Any signal below 200mV for more than 30s (typical) will assert the corresponding LOS pin. The LOS condition is cleared when the signal amplitude rises above 250mV. The LXT386 requires more than 10 and less than 255 bit periods to declare a LOS condition in accordance to ITU G.775.
3.2.2
Alarm Indication Signal (AIS) Detection
The AIS detection is performed by the receiver independent of any loopback mode. This feature is available in host mode only. Because there is no clock in data recovery mode, AIS detection will not work in that mode. AIS requires MCLK to have clock applied, since this function depends on the clock to count the number of ones in an interval.
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
3.2.2.1
E1 Mode
One detection mode suitable for both ETSI and ITU is available when the LACS register bits are cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this:
ETSI ETS300233 and G.775 detection
The AIS condition is declared when the received data stream contains less than 3 zeros within a period of 512 bits. The AIS condition is cleared when 3 or more zeros within 512 bits are detected.
3.2.2.2
T1 Mode
ANSI T1.231 detection is employed. The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This corresponds to a 99.9% ones density over a period of 5.3ms. The AIS condition is cleared when the received signal contains 9 or more zeros in any string of 8192 bits.
3.2.3
In Service Code Violation Monitoring
In unipolar I/O mode with HDB3/B8ZS decoding, the LXT386 reports bipolar violations on RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same polarity) are reported at the BPV output.
3.3
Transmitter
The four low power transmitters of the LXT386 are identical. Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O and HDB3/B8ZS/AMI encoding/decoding is selected by pulling TNEG High for more than 16 consecutive TCLK clock cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer to the Test Specifications Section for MCLK and TCLK timing characteristics. If TCLK is not supplied, the transmitter remains powered down and the TTIP/ TRING outputs are held in a High Z state. In addition, fast output tristatability is also available through the OE pin (all ports) and/or the port's OEx bit in the Output Enable Register (OER). Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS, used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings). The LXT386 also supports AMI line coding/decoding as shown in Figure 6. In Hardware mode, AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is selected by bit 4 in the GCR (Global Control Register).
Datasheet
25
LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 6. 50% AMI Encoding
TTIP Bit Cell 1 TRING 0 1
Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse shaper is bypassed if no MCLK is supplied while TCLK is pulled high. In this case TPOS and TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied and TCLK pulled high the driver enters TAOS (Transmit All Ones pattern). Note that the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability.TAOS is inhibited during Remote Loopback.
3.3.1
Transmit Pulse Shaping
The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks, spaces or if it is in transition. This well controlled dynamic impedance provides excellent return loss when used with external precision resistors ( 1% accuracy) in series with the transformer.
3.3.1.1
Hardware Mode
In hardware mode, pins LEN0-2 determine the pulse shaping as described in Table 2. The LEN settings also determine whether the operating mode is T1 or E1. Note that in T1 operation mode, all four ports will share the same pulse shaping setting. Independent pulse shaping for each channel is available in host mode
3.3.1.2
Host Mode
In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of pulse output at TTIP/TRING. Refer to Table 24 and Table 25.
26
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
.
Table 2.
LEN2 0 1 1 1 1 0
Line Length Equalizer Inputs
LEN1 1 0 0 1 1 0 LEN0 1 0 1 0 1 0 Line Length1 0 - 133 ft. ABAM 133 - 266 ft. ABAM 266 - 399 ft. ABAM 399 - 533 ft. ABAM 533 - 655 ft. ABAM Cable Loss2 0.6 dB 1.2 dB 1.8 dB 2.4 dB 3.0 dB E1 T1 Operation Mode
E1 G.703, 75 coaxial cable and 120 twisted pair cable.
1. Line length from LXT386 to DSX-1 cross-connect point. 2. Maximum cable loss at 772KHz.
3.3.2
Transmit Pulse Shaping
The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks.
3.3.2.1
Output Driver Power Supply
The output driver power supply (TVCC pins) can be either 3.3V or 5V nominal. When TVCC=5V, LXT386 drives both E1 (75/120) and T1 100 lines through a 1:2 transformer and 11/9.1 series resistors. When TVCC=3.3V, the LXT386 drives E1 (75/120) lines through a 1:2 transformer and 11 series resistor. A configuration with a 1:2 transformer and without series resistors should be used to drive T1 100 lines. Removing the series resistors for T1 applications with TVCC=3.3V, improves the power consumption of the device. See Table 35. On the other hand, series resistors in the transmit configuration improve the transmit return loss performance. Good transmit return loss performance minimizes reflections in harsh cable environments. In addition, series resistors provide protection against surges coupled to the device. The resistors should be used in systems requiring protection switching without external relays. Please refer to Figure 7 for the recommended external line circuitry.
3.3.2.2
Power Sequencing
For the LXT384, we recommend sequencing TVCC first then VCC second or at the same time as TVCC to prevent excessive current draw.
3.4
Driver Failure Monitor
The LXT386 transceiver incorporates an internal power Driver Failure Monitor (DFM) in parallel with TTIP and TRING that is capable of detecting secondary shorts without cable. DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V). This feature is available in the serial and parallel host modes but not available in the hardware mode of operation.
Datasheet
27
LXT386 -- QUAD T1/E1/J1 Transceiver
A capacitor, charged via a measure of the driver output current and discharged by a measure of the maximum allowable current, is used to detect a secondary short failure. Secondary shorted lines draw excess current, overcharging the cap. When the capacitor charge deviates outside the nominal charge window, a driver short circuit fail (DFM) is reported in the respective register by setting an interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. Note that unterminated lines of adequate length (/4) may effectively behave as short-circuits as seen by the driver and therefore trigger the DFM. Under these circumstances, the alarm should be disabled. In addition, LXT386 features output driver short-circuit protection. When the output current exceeds 100 mA, LXT386 limits the driver's output voltage to avoid damage.
3.5
Line Protection
Figure 7 on page 29 shows recommended line interface circuitry. In the receive side, the 1 k series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (70 k typical) the resistors do not affect the receiver sensitivity. In the transmit side, the Schottky diodes D1-D4 protect the output driver.While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness.
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 7. External Transmit/Receive Line Circuitry
TVCC TVCC
68F
TVCC TVCC TVS1 TVS1
1
0.1F
TVCC
TGND TGND
TVCC
D4
RT
1:2
TTIP
D3
3.3V
VCC
0.1F TVCC
2 560pF
Tx LINE
GND TRING
D2 RT T 3
D1
LXT386
(ONE CHANNEL) (ONE CHANNEL)
1k 1k 1:2 1:2 RR RR 0.22F 0.22F Rx LINE Rx LINE
RTIP RTIP
RR RR
RRING RRING
1k 1k
1 1 2 2 3 3
Common decoupling capacitor for all TVCC and TGND pins. Common decoupling capacitor for all TVCC and TGND pins. Typical value. Adjust for actual board parasitics to obtain optimum return loss. Typical value. Adjust for actual board parasitics to obtain optimum return loss. Refer to Transformer Specifications Table for transformer specifications. Refer to Transformer Specifications Table for transformer specifications.
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LXT386 -- QUAD T1/E1/J1 Transceiver
3.6
Jitter Attenuation
A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the receive or transmit path. In Hardware Mode, the JAL position is determined by the JASEL pin. The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the FIFO with the dejittered JAL clock. See Figure 8. When the FIFO is within two bits of overflowing or underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator produces a constant delay of 17 or 33 bits in the associated path (refer to test specifications). This feature can be used for hitless switching applications. This advanced digital jitter attenuator meets latest jitter attenuation specifications. See Table 3. Under software control, the low limit jitter attenuator corner frequency depends on FIFO length and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode.
Table 3.
Jitter Attenuation Specifications
T1 AT&T Pub 62411 GR-253-CORE
1
E1 ITU-T G.736 ITU-T G.7423 ITU-T G.7834
TR-TSY-0000092
ETSI CTR12/13 BAPT 220
1. 2. 3. 4.
Category I, R5-203. Section 4.6.3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper.
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QUAD T1/E1/J1 Transceiver -- LXT386
Figure 8. Jitter Attenuator Loop
FIFO64
TPOS RPOSi TNEG RNEGi
TPOSo RPOS
FIFO
IN CK OUT CK
TNEGo RNEG
TCLK RCLKi
IN
DPLL
OUT
TCLK RCLK
JASEL0-1
JASEL0-1
MCLK
x 32
JACF
GCR control bits
3.7
Loopbacks
The LXT386 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP registers are employed.
3.7.1
Analog Loopback
When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver inputs (RTIP & RRING) as shown in Figure 9. Data and clock are output at RCLK, RPOS & RNEG pins for the corresponding transceiver. Note that signals on the RTIP & RRING pins are ignored during analog loopback.
Figure 9. Analog Loopback
HDB3/B8ZS Encoder*
TCLK TPOS TNEG
JA*
Timing & Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
JA*
Timing Recovery
RTIP RRING
* If Enabled
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LXT386 -- QUAD T1/E1/J1 Transceiver
3.7.2
Digital Loopback
The digital loopback function is available in software and hardware mode. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS & RNEG pins (Figure 10). The data presented on TCLK, TPOS & TNEG is also output on the TTIP & TRING pins. Note that signals on the RTIP & RRING pins are ignored during digital loopback.
Figure 10. Digital Loopback
TCLK TPOS TNEG HDB3/B8ZS Encoder*
JA*
Timing & Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
JA*
Timing Recovery
RTIP RRING
* If Enabled
3.7.3
Remote Loopback
During remote loopback (Figure 11) the RCLK, RPOS & RNEG outputs routed to the transmit circuits and output on the TTIP & TRING pins. Note that input signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback.
Figure 11. Remote Loopback
HDB3/B8ZS Encoder*
TCLK TPOS TNEG
JA*
Timing & Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
JA*
Timing Recovery
RTIP RRING
* If Enabled
Note:
In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback.
3.7.4
Transmit All Ones (TAOS)
In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles. In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register. Note: The TAOS generator uses MCLK as a timing reference, therefore TAOS doesn't work in data recovery mode. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. DLOOP does not function with TAOS active.
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Figure 12. TAOS Data Path
MCLK TAOS mode HDB3/B8ZS Encoder* TCLK TPOS TNEG Timing & Control TTIP TRING (ALL 1's)
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
JA*
Timing Recovery
RTIP RRING
* If Enabled
Figure 13. TAOS with Analog Loopback
MCLK TAOS Mode TCLK TPOS TNEG HDB3/B8ZS Encoder* Timing & Control TTIP TRING (ALL 1's)
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
JA*
Timing Recovery
RTIP RRING
* If Enabled
3.8
G.772 Performance Monitoring
The LXT386 can be configured as a quad line interface unit with all channels working as regular transceivers. In applications using only three channels, the fourth channel can be configured to monitor any of the remaining channels inputs or outputs. The monitoring is non-intrusive per ITUT G.772. Figure 2 on page 8 illustrates this concept. The monitored line signal (input or output) goes through channel 0 clock and data recovery. The signal can be observed digitally at the RCLK/RPOS/RNEG outputs. This feature can also be used to create timing interfaces derived from an E1 or T1 signal. In addition, channel 0 can be configured to a Remote Loopback while in monitoring mode (TCLK0 must be active in order for this operation to take place). This will output the same data as in the signal being monitored at the channel 0 output (TTIP/TRING). The output signal can then be connected to a standard test equipment with a T1/E1 electrical interface for monitoring purposes (non-intrusive monitoring).
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LXT386 -- QUAD T1/E1/J1 Transceiver
3.9
Hitless Protection Switching (HPS)
The LXT386 transceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Please refer to Application Note 119 for guidelines for implementing redundancy systems for both T1 and E1 operation using the LXT380/1/4/6.
3.10
Operation Mode Summary
Table 4 lists summarizes all LXT386 hardware settings and corresponding operating modes.
Table 4.
MCLK Clocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked L L L L L L L H H H H H H H H
Operation Mode Summary
TCLK Clocked Clocked Clocked L L L H H H Clocked Clocked Clocked H H H L Clocked Clocked Clocked L L H H H LOOP1 Open L H Open L H Open L H Open L H Open L H X Open L H Open L Open L H Receive Mode Data/Clock recovery Data/Clock recovery Data/Clock recovery Data/Clock recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Data/Clock Recovery Power Down Power Down Power Down Power Down Power Down Power Down Power Down Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Data Recovery Transmit Mode Pulse Shaping ON Pulse Shaping ON Pulse Shaping ON Power down Power down Power down Transmit All Ones Pulse Shaping ON Transmit All Ones Pulse Shaping ON Pulse Shaping ON Pulse Shaping ON Pulse Shaping OFF Pulse Shaping OFF Pulse Shaping OFF Power down Pulse Shaping ON Pulse Shaping OFF Pulse Shaping ON Power down Pulse Shaping OFF Pulse Shaping OFF Pulse Shaping OFF Pulse Shaping OFF Loopback No Loopback Remote Loopback Analog Loopback No Loopback No effect on op. No Analog Loopback No Loopback Remote Loopback No effect on op. No Loopback No Remote Loopback No effect on op. No Loopback No Remote Loop No effect on op. No Loopback No Loopback Remote Loopback Analog Loopback No Loopback Remote Loopback No Loopback Remote Loopback Analog Loopback
1. Hardware mode only.
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QUAD T1/E1/J1 Transceiver -- LXT386
3.11
Interfacing with 5V logic
The LXT386 can interface directly with 5V logic. The internal input pads are tolerant to 5V outputs from TTL and CMOS family devices.
3.12
Parallel Host Interface
The LXT386 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is generic and is designed to support both non-multiplexed and multiplexed address/data bus systems for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different operating modes as shown in Table 5.
Table 5.
Microprocessor Parallel Interface Selection
MUX Low Low High High MOT/INTL Low High Low High Operating Mode Motorola Non-Multiplexed Intel Non-Multiplexed Motorola Multiplexed Intel Multiplexed
The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS, INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low signal acknowledges the acceptance of the write data. In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed. While Low the microprocessor must insert wait states. This allows the LXT386 to interface with wait-state capable micro controllers, independent of the processor bus speed. To activate this function a reference clock is required on the MCLK pin. There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the reset register. Because of timing issues, the RDY line remains high after the first part of the cycle is done, not signalling write cycle completion with another transition low. In this mode, add 2 microseconds of delay, overall 3 microseconds from CS low to end of cycle, to allow the reset cycle to completely initialize the device before proceeding. An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to the microprocessor. The LXT386 has a 5 bit address bus and provides 18 user accessible 8-bit registers for configuration, alarm monitoring and control of the chip.
3.12.1
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode the falling edge of DS is used to latch the address information on the address bus. In multiplexed operation the address on the multiplexed address data bus is latched into the device with the falling edge of AS. In non-multiplexed mode, AS should be pulled High.
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LXT386 -- QUAD T1/E1/J1 Transceiver
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/ W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising edge on DS. Both cycles require the CS signal to be Low and the Address pins to be actively driven by the microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT386.
3.12.2
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT386 supports nonmultiplexed interfaces with separate address and data pins when MUX is asserted Low, and multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS is used as the WR signal. A read cycle is indicated to the LXT386 when the processor asserts RD Low while the WR signal is held High. A write operation is indicated to the LXT386 by asserting WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
3.13
Interrupt Handling
Interrupt Sources
There are three interrupt sources: 1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT386's analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific LOS status bit to indicate presence or absence of a LOS condition. 2. Status change in the Driver Failure Monitoring (DFM) status register (05H). The LXT386's smart power driver circuit continuously monitors the output drivers signal and updates the specific DFM status bit to indicate presence or absence of a secondary driver short circuit condition. 3. Status change in the Alarm Indication Signal (AIS) status register (13H).The LXT386's receiver monitors the incoming data stream and updates the specific AIS status bit to indicate presence or absence of a AIS condition.
3.13.1
Interrupt Enable
The LXT386 provides a latched interrupt output (INT). An interrupt occurs any time there is a transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM and AIS interrupt enable registers (respectively). Writing a logic "1" into the mask register will enable the respective bit in the respective Interrupt status register to generate an interrupt. The power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers. Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers. When there is a transition on any enabled bit in a status register, the associated bit of the interrupt status register is set and an interrupt is generated (if one is not already pending). When an interrupt
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QUAD T1/E1/J1 Transceiver -- LXT386
occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR operation.
3.13.2
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register clears the "sticky" bit set by the interrupt. Automatically clearing the register prepares it for the next interrupt. The ISR should then read the corresponding status monitor register to obtain the current status of the device. Note that there are three status monitor registers: the LOS (04H), the DFM (05H) and the AIS (013H). Reading either status monitors register will clear its corresponding interrupts on the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes High.
3.14
Serial Host Mode
The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC/2. Figure 14 shows the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/ Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte address specific registers (the address decoder ignores bits A7-6). The data byte depends on both the value of bit R/W and the address of the register as set in the Command/Address byte.
Figure 14. Serial Host Mode Timing
CS
SCLK
ADDRESS/COMMAND BYTE
INPUT DATA BYTE
SDI
R/W
A1
A2
A3
A4
A5
A6 X
A7 X
D0
D1
D2
D3
D4
D5
D6
D7
SDO - REMAINS HIGH Z
SDO IS DRIVEN IF R/W = 1
R/W = 1: Read from the LXT386 R/W = 0: Write to the LXT386 X = Don't care
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LXT386 -- QUAD T1/E1/J1 Transceiver
4.0
Table 6.
Name
Register Descriptions
Serial and Parallel Port Register Addresses
Address Symbol Serial Port A7-A1 xx00000 xx00001 xx00010 xx00011 xx00100 xx00101 xx00110 xx00111 xx01000 xx01001 xx01010 xx01011 xx01100 xx01101 xx01110 xx01111 xx10000 xx10001 xx10010 xx10011 xx10100 xx10101 Parallel Port A7-A0 xxx00000 xxx00001 xxx00010 xxx00011 xxx00100 xxx00101 xxx00110 xxx00111 xxx01000 xxx01001 xxx01010 xxx01011 xxx01100 xxx01101 xxx01110 xxx01111 xxx10000 xxx10001 xxx10010 xxx10011 xxx10100 xxx10101 Mode
ID Register Analog Loopback Remote Loopback TAOS Enable LOS Status Monitor DFM Status Monitor LOS Interrupt Enable DFM Interrupt Enable LOS Interrupt Status DFM Interrupt Status Software Reset Register Performance Monitoring Digital Loopback LOS/AIS Criteria Selection Automatic TAOS Select Global Control Register Pulse Shaping Indirect Address Register Pulse Shaping Data Register Output Enable Register AIS Status Register AIS Interrupt Enable AIS Interrupt Status
ID ALOOP RLOOP TAOS LOS DFM LIE DIE LIS DIS RES MON DL LOSC ATS GCR PSIAD PSDAT OER AIS AISIE AISIS
R R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R
Table 7.
Register Bit Names
Register Bit Sym ID ALOOP RLOOP TAOS RW R R/W R/W R/W 7 ID7 6 ID6 5 ID5 4 ID4 3 ID3 AL3 RL3 TAOS3 2 ID2 AL2 RL2 TAOS2 1 ID1 AL1 RL1 TAOS1 0 ID0 AL0 RL0 TAOS0
Name ID Register Analog Loopback Remote Loopback TAOS Enable
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QUAD T1/E1/J1 Transceiver -- LXT386
Table 7.
Register Bit Names (Continued)
Register Bit Sym LOS DFM LIE DIE LIS DIS RES MON DL LACS ATS GCR PSIAD PSDAT OER AIS AISIE AISIS RW R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R 7 reserve d reserve d reserve d reserve d 6 reserve d RAISE N reserve d reserve d 5 reserve d CDIS reserve d reserve d 4 reserve d CODEN reserve d reserve d 3 LOS3 DFM3 LIE3 DIE3 LIS3 DIS3 RES3 A3 DL3 LACS3 ATS3 FIFO64 reserve d reserve d OE3 AIS3 AISIE3 AISIS3 2 LOS2 DFM2 LIE2 DIE2 LIS2 DIS2 RES2 A2 DL2 LACS2 ATS2 JACF LENAD2 LEN2 OE2 AIS2 AISIE2 AISIS2 1 LOS1 DFM1 LIE1 DIE1 LIS1 DIS1 RES1 A1 DL1 LACS1 ATS1 JASEL1 LENAD1 LEN1 OE1 AIS1 AISIE1 AISIS1 0 LOS0 DFM0 LIE0 DIE0 LIS0 DIS0 RES0 A0 DL0 LACS0 ATS0 JASEL0 LENAD0 LEN0 OE0 AIS0 AISIE0 AISIS0
Name LOS Status Monitor DFM Status Monitor LOS Interrupt Enable DFM Interrupt Enable LOS Interrupt Status DFM Interrupt Status Software Reset Register Performance Monitoring Digital Loopback LOS/AIS Criteria Select Automatic TAOS Select Global Control Register Pulse Shaping Indirect Address Register Pulse Shaping Data Register Output Enable Register AIS Status Register AIS Interrupt Enable AIS Interrupt Status
Table 8.
Bit
ID Register, ID (00H)
Name Function This register contains a unique revision code and is mask programmed.
7-0
ID7-ID0
For Revision A1, ID register = 00h For Revision B1, ID register = 21h For Revision B2, ID register = 22h
Table 9.
Bit 3-0
Analog Loopback Register, ALOOP (01H)
Name AL3-AL0 Function Setting a bit to "1" enables analog local loopback for transceivers 3- 0 respectively.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 10. Remote Loopback Register, RLOOP (02H)
Bit 3-0 Name RL3-RL0 Function Setting a bit to "1" enables remote loopback for transceivers 3-0 respectively.
Table 11. TAOS Enable Register, TAOS (03H)
Bit1 3-0 7-4 Name TAOS3-TAOS0 Function2 Setting a bit to "1" causes a continuous stream of marks to be sent out at the TTIP and TRING pins of the respective transceiver 3-0. Write "0" to these positions for normal operation.
1. On power up all register bits are set to "0". 2. MCLK is used as timing reference. If MCLK is not available then the channel TCLK is used as the reference. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High)
Table 12. LOS Status Monitor Register, LOS (04H)
Bit1 3-0 Name LOS3-LOS0 Function Respective bit(s) are set to "1" every time the LOS processor detects a valid loss of signal condition in transceivers 3-0.
1. On power up all register bits are set to "0". Any change in the state causes an interrupt. All LOS interrupts are cleared by a single read operation.
Table 13. DFM Status Monitor Register, DFM (05H)
Bit1 Name Function Respective bit(s) are set to "1" every time the short circuit monitor detects a valid secondary output driver short circuit condition in transceivers 3-0. Note that DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V).
3-0
DFM3-DFM0
1. On power-up all the register bits are set to "0". All DFM interrupts are cleared by a single read operation.
Table 14. LOS Interrupt Enable Register, LIE (06H)
Bit1 3-0 7-4 Name LIE3-LIE0 Function Transceiver 3-0 LOS interrupts are enabled by writing a "1" to the respective bit. Write "0" to these positions for normal operation.
1. On power-up all the register bits are set to "0"and all interrupts are disabled.
Table 15. DFM Interrupt Enable Register, DIE (07H)
Bit1 3-0 7-4 Name DIE3-DIE0 Function Transceiver 3-0 DFM interrupts are enabled by writing a "1" to the respective bit. Write "0" to these positions for normal operation.
1. On power-up all the register bits are set to "0"and all interrupts are disabled.
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Table 16. LOS Interrupt Status Register, LIS (08H)
Bit 3-0 Name LIS3-LIS0 Function These bits are set to "1" every time a LOS status change has occurred since the last clear interrupt in transceivers 3-0 respectively.
Table 17. DFM Interrupt Status Register, DIS (09H)
Bit 3-0 Name DIS3-DIS0 Function These bits are set to "1" every time a DFM status change has occurred since the last cleared interrupt in transceivers 3-0 respectively.
Table 18. Software Reset Register, RES (0AH)
Bit Name Function Writing to this register initiates a 1 microsecond reset cycle, except for Intel nonmultiplexed mode. When using Intel non-multiplexed host mode, extend cycle time to 2 microseconds. Please refer to Host Mode section for more information. This operation sets all LXT386 registers to their default values.
3-0
RES3-RES0
Table 19. Performance Monitoring Register, MON (0BH)
Bit 3-0 4-7 Name A3:A0 reserved Function Protected Monitoring selection. See Table 1 on page 11. Reserved.
Table 20. Digital Loopback Register, DL (0CH)
Bit1 3-0 Name DL3-DL0 Function2 Setting a bit to "1" enables digital loopback for the respective transceiver.
1. On power up all register bits are set to "0". 2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on TPOS/TNEG/TCKLK is looped back to RPOS/RNEG/RCLK.
Table 21. LOS/AIS Criteria Register, LCS (0DH)
Bit1 Name T1 Mode2 Don't care. T1.231 compliant LOS/AIS detection is used. 3-0 LCS3-LCS01 E1 Mode Setting a bit to "1" selects the ETS1 300233 LOS. Setting a bit to "0" selects G.775 LOS mode. AIS works correctly for both ETSI and ITU when the bit is cleared to "0". See errata revision 10.3 or higher for a way to implement ETSI LOS and AIS. 1. On power-on reset the register is set to "0". 2. T1 or E1 operation mode is determined by the PSDR settings. Function2
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 22. Automatic TAOS Select Register, ATS (0EH)
Bit1 3-0 7-4 Name ATS3-ATS0 Function Setting a bit to "1" enables automatic TAOS generation whenever a LOS condition is detected in the respective transceiver. Write "0" to these positions for normal operation.
1. On power-on reset the register is set to "0". 2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High)
Table 23. Global Control Register, GCR (0FH)
Bit1 0 Name JASEL0 Function These bits determine the jitter attenuator position: JASEL0 1 1 JASEL1 1 0 JASEL1 0 1 x JA Position Transmit Path Receive Path Disabled
2
JACF
This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter Attenuator specifications for details (Table 41 on page 58). This bit determines the jitter attenuator FIFO depth: 0 = 32 bit 1 = 64 bit This bit selects the zero suppression code for unipolar operation mode: 0 = B8ZS/HDB3 (T1/E1 respectively) 1 = AMI This bit controls enables/disables the short circuit protection feature: 0 = enabled 1 = disabled This bit controls automatic AIS insertion in the receive path when LOS occurs: 0 = Receive AIS insertion disabled on LOS 1 = RPOS/RNEG = AIS on LOS Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS interrupts when changing this bit value to prevent inadvertent interrupts.
3
FIFO64
4
CODEN
5
CDIS
6
RAISEN
7
-
Reserved.
1. On power-on reset the register is set to "0".
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Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H)
Bit1 Name Function The three bit value written to these bits determine the channel to be addressed: 0-2 LENAD 0-2 0H = channel 0 1H = channel 1 2H = channel 2 3H = channel 3 Data can be read from (written to) the Pulse Shaping Data Register (PSDAT). 3-7 Reserved.
1. On power-on reset the register is set to "0".
Table 25. Pulse Shaping Data Register, PSDAT (11H)
Bit Name Function LEN0-2 determine the LXT386 operation mode: T1 or E1. In addition, for T1 operation, LEN2-0 set the pulse shaping to meet the T1.102 pulse template at the DSX-1 crossconnect point for various cable lengths: LEN2 0-2 LEN 0-2 1, 3 0 1 1 1 1 0 3-7 Reserved. LEN1 1 0 0 1 1 0 LEN0 1 0 1 0 1 0 Line Length 0 - 133 ft. ABAM 133 - 266 ft. ABAM 266 - 399 ft. ABAM 399 - 533 ft. ABAM 533 - 655 ft. ABAM Cable Loss2 0.6 dB 1.2 dB 1.8 dB 2.4 dB 3.0 dB E1 T1 Operation Mode
E1 G.703, 75 coaxial cable and 120 twisted pair cable.
1. On power-on reset the register is set to "0". 2. Maximum cable loss at 772 KHz. 3. When reading LEN, bit values appear inverted. "B1" revision silicon will fix this so the bits read back correctly.
Table 26. Output Enable Register, OER (12H)
Bit1 3-0 Name OE3 - OE0 Function Setting a bit to "1" tristates the output driver of the corresponding transceiver.
1. On power-up all the register bits are set to "0".
Table 27. AIS Status Monitor Register, AIS (13H)
Bit1 3-0 Name AIS3-AIS0 Function Respective bit(s) are set to "1" every time the receiver detects a AIS condition in transceivers 3-0.
1. On power-up all the register bits are set to "0". All AIS interrupts are cleared by a single read operation.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 28. AIS Interrupt Enable Register, AISIE (14H)
Bit1 3-0 7-4 Name AISIE3-AISIE0 Function Transceiver 3-0 AIS interrupts are enabled by writing a "1" to the respective bit. Write "0" to these positions for normal operation.
1. On power-up all the register bits are set to "0".
Table 29. AIS Interrupt Status Register, AISIS (15H)
Bit1 3-0 Name AISIS3-AISIS0 Function These bits are set to "1" every time a AIS status change has occurred since the last clear interrupt in transceivers 3-0 respectively.
1. On power-up all the register bits are set to "0".
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5.0
5.1
JTAG Boundary Scan
Overview
The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT386 also includes analog test port capabilities. This feature provides access to the TIP and RING signals in each channel (transmit and receive). This way, the signal path integrity across the primary winding of each coupling transformer can be tested.
5.2
Architecture
Figure 15 represents the LXT386 basic JTAG architecture. The LXT386 JTAG architecture includes a TAP Test Access Port Controller, data registers and an instruction register. The following paragraphs describe these blocks in detail.
Figure 15. LXT386 JTAG Architecture
Boundry Scan Data Register BSR Analog Port Scan Register ASR Device Identification Register IDR Bypass Register BYR Instruction Register IR
TDI
MUX
TDO
TCK TMS TRST
TAP Controller
5.3
TAP Controller
The TAP controller is a 16 state synchronous state machine controlled by the TMS input and clocked by TCK ( Figure 16).The TAP controls whether the LXT386 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 30 describes in detail each of the states represented in Figure 16.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 30. TAP State Description
State Test Logic Reset Run -Test/Idle Capture - DR Shift - DR Update - DR Capture - IR Shift - IR Update - IR Pause - IR Pause - DR Exit1 - IR Exit1 - DR Exit2 - IR Exit2 - DR Description In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the instruction register is set to the ICODE instruction. The TAP controller stays in this state as long as TMS is low. Used to perform tests. The Boundary Scan Data Register (BSR) is loaded with input pin data. Shifts the selected test data registers by one stage tword its serial output. Data is latched into the parallel output of the BSR when selected. Used to load the instruction register with a fixed instruction. Shifts the instruction register by one stage. Loads a new instruction into the instruction register. Momentarily pauses shifting of data through the data/instruction registers.
Temporary states that can be used to terminate the scanning process.
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QUAD T1/E1/J1 Transceiver -- LXT386
Figure 16. JTAG State Diagram
1
TEST-LOGIC RESET 0
0 RUN TEST/IDLE
1
SELECT-DR 0 1
1
SELECT-IR 0 1
1
CAPTURE-DR 0 0 SHIFT-DR 1 1
CAPTURE-IR 0 0 SHIFT-IR 1 1
EXIT1-DR 0
EXIT1-IR 0
0 PAUSE-DR 1 0 0 PAUSE-IR 1
0
EXIT2-DR 1
EXIT2-IR 0
UPDATE-DR 1 0
UPDATE-IR 1 0
5.4
JTAG Register Description
The following paragraphs describe each of the registers represented in Figure 15.
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LXT386 -- QUAD T1/E1/J1 Transceiver
5.4.1
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register. Bidirectional pins or tristatable pins require more than one position in the register. Table 1 shows the BSR scan cells and their functions. Data into the BSR is shifted in LSB first.
Example 1. Boundary Scan Register (BSR)
Bit # 0 Pin Signal LOS3 RNEG3 N/A RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 LOS2 RNEG2 N/A RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 MCLK MODE INT N/A ACK ALE OE CLKE A0 A1 A2 A3 A4 LOOP0 I/O Type O O O O I I I O O O O I I I I I O O I I I I I I I I I/O Bit Symbol LOS3 RNEG3 HIZ3 RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 LOS2 RNEG2 HIZ2 RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 MCLK MODE INTRUPTB SDORDYENB SDORDY ALE OE CLKE A0 A1 A2 A3 A4 PADD0 SDORDYENB controls the ACK pin. Setting SDORDYENB to "0" enables output on ACK pin. Setting SDORDYENB to "1" tristates the pin. HIZ2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting HIZ2 to "0" enables output on the pins. Setting HIZ2 to "1" tristates the pins. HIZ3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting HIZ3 to "0" enables output on the pins. Setting HIZ3 to "1" tristates the pins. Comments
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QUAD T1/E1/J1 Transceiver -- LXT386
Example 1. Boundary Scan Register (BSR) (Continued)
Bit # Pin Signal LOOP0 LOOP1 LOOP1 LOOP2 LOOP2 LOOP3 LOOP3 LOOP4 LOOP4 LOOP5 LOOP5 LOOP6 LOOP6 LOOP7 I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Bit Symbol PDO0 PADI1 PDO1 PADI2 PDO2 PADI3 PDO3 PADI4 PDO4 PADI5 PDO5 PADI6 PDO6 PADI7 PDOENB controls the LOOP0 through LOOP7 pins. N/A PDOENB Setting PDOENB to "0" configures the pins as outputs. The output value to the pin is set in PDO[0..7]. Setting PDOENB to "1" tristates all the pins. The input value to the pins can be read in PADD[0..7]. LOOP7 CS MUX RESET MOT/INTL R/W DS TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 N/A RNEG1 LOS1 TCLK0 TPOS0 TNEG0 RCLK0 I/O I I I I I I I I I O O O O I I I O PDO7 CSB MUX RSTB IMB RDB WRB TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 HIZ1 RNEG1 LOS1 TCLK0 TPOS0 TNEG0 RCLK0 HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to "0" enables output on the pins. Setting HIZ1 to "1" tristates the pins. Comments
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LXT386 -- QUAD T1/E1/J1 Transceiver
Example 1. Boundary Scan Register (BSR) (Continued)
Bit # Pin Signal RPOS0 N/A RNEG0 LOS0 I/O Type O O O Bit Symbol RPOS0 HIZ0 RNEG0 LOS0 HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZ0 to "0" enables output on the pins. Setting HIZ0 to "1" tristates the pins. Comments
5.5
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT386 revision. The register is arranged per IEEE 1149.1 and is represented in Table 31. Data into the IDR is shifted in LSB first.
Table 31. Device Identification Register (IDR)
Bit # 31 - 28 27 - 12 11 - 1 0 Comments Revision Number Part Number Manufacturer Number Set to "1"
5.5.1
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the TDO output.
5.5.2
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into the ASR is shifted in LSB first. Table 32 shows the 8 possible control codes and the corresponding operation on the analog port. The Analog Test Port can be used to verify continuity across the coupling transformers primary winding. The Analog Test Port can be used to verify continuity across the coupling transformer's primary winding as shown in Figure 17. By applying a stimulus to the AT1 input, a known voltage will appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface.
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Table 32. Analog Port Scan Register (ASR)
ASR Control Code 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 RTIP0 RTIP1 RTIP2 RTIP3 Reserved Reserved Reserved Reserved AT1 Forces Voltage To: TTIP0 TTIP1 TTIP2 TTIP3 Reserved Reserved Reserved Reserved RRING0 RRING1 RRING2 RRING3 AT2 Senses Voltage From: TRING0 TRING1 TRING2 TRING3
5.5.3
Instruction Register (IR)
The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 33 shows the valid instruction codes and the corresponding instruction description.
Table 33. Instruction Register (IR)
Instruction EXTEST INTEST_ANALOG SAMPLE / PRELOAD IDCODE BYPASS Code # 000 010 100 110 111 Comments Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR. Output pins values are loaded from the BSR. Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and AT2. Refer to Table 32. Connects the BSR to TDI and TDO. The normal path between the LXT386 logic and the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins. Connects the IDR to the TDO pin. Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass Register.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 17. Analog Test Port Application
JTAG Port ASR Register
RTIP3 RRING3 TTIP3 TRING3 RTIP2 Transceiver 3
TTIP2 TRING2
1K
RTIP0 RRING0 Transceiver 0
1K
AT2 AT1
52
Analog Mux
RRING2
Transceiver 2
Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
6.0
Note:
Test Specifications
Table 34 through Table 53 and Figure 18 through Figure 33 represent the performance specifications of the LXT386 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 36 through Table 53 are guaranteed over the recommended operating conditions specified in Table 35.
Table 34. Absolute Maximum Ratings
Parameter DC supply voltage DC supply voltage Input voltage on any digital pin Input voltage on RTIP, RRING1 ESD voltage on any Pin 2 Transient latch-up current on any pin Input current on any digital pin
3 3
Symbol Vcc Tvcc 0-3 Vin Vin Vin Iin Iin Iin Iin Tstor PP Tcase Tcase
Min -0.5 -0.5 GND-0.5 GND-0.5 2000
Max 4.0 7.0 5.5 VCC + 0.5 VCC + 0.5 - 100
Unit V V V V V mA mA mA mA
-10 - - -65
10 100 100 +150 830
DC input current on TTIP, TRING
DC input current on RTIP, RRING 3 Storage temperature Maximum power dissipation in package Case Temperature, 100 pin LQFP package Case Temperature, 160 pin PBGA package
C
mW
- -
120 120
C C
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Referenced to ground. 2. Human body model. 3. Constant input current.
Table 35. Recommended Operating Conditions
Parameter Digital supply voltage (VCC) Transmitter supply voltage, TVCC=5V nominal Transmitter supply voltage, TVCC=3.3V nominal Ambient operating temperature LEN Sym VCC TVCC TVCC Ta Min 3.135 4.75 3.135 -40 Typ 3.3 5.0 3.3 25 Max 3.465 5.25 3.465 +85 Unit V V V Test Condition 3.3V 5% 5V 5% 3.3V 5%
C
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 35. Recommended Operating Conditions (Continued)
Parameter Average Transmitter Power Supply Current, T1 Mode 1, 2, 3 Average Digital Power Supply Current 1, 4 Output load at TTIP and TRING LEN Sym Min Typ 215 110 50 - Max 245 60 - Unit mA mA mA Test Condition 100% 1's 50% 1's
ITVCC IVCC Rl
25
Device Power Consumption Mode TVCC Load 75 E1 3.3V 120 100 75 E1 5.0V 120 100 000 101-111 1400 mW 100% 1's 830 810 mW mW 100% 1's 50% 1's 540 mW 50% 1's 000 101-111 000 930 mW 100% 1's 610 1025 mW mW 100% 1's 50% 1's 550 600 mW mW 100% 1's 50% 1's 400 mW 50% 1's LEN 000 680 mW 100% 1's Typ 440 Max1,2 Unit mW Test Condition 50% 1's
T13
3.3V
T13
5.0V
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
Table 36. DC Characteristics
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage
1
Sym Vih Vil Voh Vol Vinl Vinm Vinh Iinl Iinh
Min 2 - 2.4 - - 1/3VCC+0.2 2/3VCC+0.2 - -
Typ - - - - - 1/2VCC - - -
Max - 0.8 VCC 0.4 1/3VCC-0.2 2/3VCC-0.2 - 50 50
Unit V V V V V V V A A
Test Condition
IOUT= 400A IOUT= 1.6mA
1
Low level input voltage MODE, LOOP0-3 and JASEL Midrange level input voltage High level input voltage Low level input current High level input current
1. Output drivers will output CMOS logic levels into CMOS loads.
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QUAD T1/E1/J1 Transceiver -- LXT386
Table 36. DC Characteristics (Continued)
Parameter Input leakage current Tri state leakage current Tri state output current Line short circuit current Input Leakage (TMS, TDI, TRST) Sym Iil Ihz Ihz - - Min -10 -10 - - - - - - Typ Max +10 +10 1 50 50 Unit A A A mA RMS A TTIP, TRING 2 x 11 series resistors and 1:2 transformer Test Condition
1. Output drivers will output CMOS logic levels into CMOS loads.
Table 37. E1 Transmit Transmission Characteristics
Parameter Output pulse amplitude Peak voltage of a space 75 120 75 120 Sym - - - - - - 15 - 15 15 15 - - 15 15 - 0.95 1:2 17 17 17 20 20 20 0.030 2 7 0.050 - - dB dB dB dB dB dB U.I. U.I. JA Disabled Unipolar mode 1. Guaranteed by design and other correlation methods. U.I. Tx path TCLK is jitter free Using components in the LXD384 evaluation board. Using components in the LXD384 evaluation board. Min 2.14 2.7 -0.237 -0.3 -1 Typ 2.37 3.0 Max 2.60 3.3 0.237 0.3 +1 200 1.05 Unit V V V V % mV For 17 consecutive pulses At the nominal half amplitude Rt = 11 1% Test Condition Tested at the line side
Transmit amplitude variation with supply Difference between pulse sequences Pulse width ratio of the positive and negative pulses Transmit transformer turns ratio for 75/120 characteristic impedance Transmit return loss 75 coaxial cable1 Transmit return loss 120 twisted pair cable1 51kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz 51kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz
Transmit intrinsic jitter; 20Hz to 100kHz Bipolar mode Transmit path delay
Table 38. E1 Receive Transmission Characteristics
Parameter Permissible cable attenuation Receiver dynamic range Signal to noise interference margin Sym - DR S/I Min - 0.5 -15 Typ - - - Max 12 - - Unit dB Vp dB Per G.703, O.151 @ 6 dB cable Attenuation Test Condition @1024 kHz
1. Guaranteed by design and other correlation methods.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 38. E1 Receive Transmission Characteristics (Continued)
Parameter Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset Low limit input jitter tolerance 1 1Hz to 20Hz 20Hz to 2.4kHz 18kHz to 100kHz - - - - Sym SRE - - - - - Min 43 - - - - 12.5% 36 1.5 0.2 - - - 20 - 20 20 - - - - 10 - 30 - 0.040 1 6 - 255 0.0625 - 70 - 20 - 1 - - - Typ 50 150 200 50 32 2048 - Max 57 - - - - - Unit % mV mV mV - - U.I. U.I. U.I. k % k dB dB dB s marks U.I. U.I. JA Disabled Unipolar mode U.I. Measured against nominal impedance using components in the LXD384 evaluation board. Data recovery mode Data recovery mode Wide band jitter G.775 recommendation ETSI 300 233 specification 1's density G735 recommendation Note 1 Cable Attenuation is 6 dB @1.024 MHz Test Condition Rel. to peak input voltage
Differential receiver input impedance Input termination resistor tolerance Common mode input impedance to ground 51 kHz - 102 kHz Input return loss1 102 - 2048 kHz 2048kHz - 3072 kHz LOS delay time LOS reset Receive intrinsic jitter, RCLK output Receive path delay Bipolar mode
1. Guaranteed by design and other correlation methods.
Table 39. T1 Transmit Transmission Characteristics
Parameter Output pulse amplitude Peak voltage of a space Driver output impedance1 Transmit amplitude variation with power supply Ratio of positive to negative pulse amplitude Difference between pulse sequences Pulse width variation at half amplitude 10Hz - 8KHz Jitter added by Transmitter1 8KHz - 40KHz 10Hz - 40KHz Wide Band - - - Sym - - - - - - - Min 2.4 -0.15 - -1 0.95 - - Typ 3.0 - 1 - - - - Max 3.6 +0.15 - +1 1.05 200 20 0.020 0.025 0.025 0.050 UIpk-pk AT&T Pub 62411 TCLK is jitter free. Unit V V Test Condition Measured at the DSX
% - mV ns
@ 772 KHz
T1.102, isolated pulse For 17 consecutive pulses, GR-499-CORE
1. Guaranteed by design and other correlation methods. 2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1's pattern.
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Table 39. T1 Transmit Transmission Characteristics (Continued)
Parameter Output power levels2 @ 772 KHz @ 1544 KHz 51kHz to 102 kHz Transmit return loss 1 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Bipolar mode Transmit path delay Unipolar mode 7 U.I. - Sym Min 12.6 -29 15 15 15 Typ Max Unit dBm dBm dB - dB dB U.I. JA Disabled Test Condition T1.102 - 1993 Referenced to power at 772 KHz With transmit series resistors (TVCC=5V). Using components in the LXD384 evaluation board.
-
-
17.9
21 21 21 2
1. Guaranteed by design and other correlation methods. 2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1's pattern.
Table 40. T1 Receive Transmission Characteristics
Parameter Permissible cable attenuation Receiver dynamic range Signal to noise interference margin Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset Low limit input jitter tolerance 1 0.1Hz to 1Hz 4.9Hz to 300Hz 10KHz to 100KHz Sym - DR S/I SRE - - - - - Min - 0.5 -16.5 63 - - - 100 12.5% 138 28 0.4 20 20 20 1
Typ - - - 70 150 200 50 175 - 70
Max 12 - - 77 - - - 250 - 1
Unit dB Vp dB % mV mV mV - - U.I. U.I. U.I. k % k dB
Test Condition @ 772 KHz
@ 655 ft. of 22 ABAM cable Rel. to peak input voltage
T1.231 - 1993 1's density AT&T Pub. 62411 @772 kHz
Differential receiver input impedance Input termination resistor tolerance Common mode input impedance to ground 51 KHz - 102 KHz Input return loss1 102 - 2048 KHz 2048 KHz - 3072 KHz LOS delay time LOS reset Receive intrinsic jitter, RCLK output Receive path delay Bipolar mode Unipolar mode
20
-
-
-
dB dB
Measured against nominal impedance. Using components in the LXD384 evaluation board. Data recovery mode Data recovery mode Wide band jitter JA Disabled
10 -
30 0.035 1 6
255 0.0625
s U.I. U.I. U.I.
-
1. Guaranteed by design and other correlation methods.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 41. Jitter Attenuator Characteristics
Parameter 32bit FIFO JACF = 0 64bit E1 jitter attenuator 3dB corner frequency, host mode1 JACF = 1 64bit FIFO 32bit FIFO JACF = 0 64bit T1 jitter attenuator 3dB corner frequency, host mode1 JACF = 1 64bit FIFO Jitter attenuator 3dB corner frequency, hardware mode1 E1 T1 32bit FIFO Data latency delay 64bit FIFO 32bit Input jitter tolerance before FIFO overflow or underflow FIFO 64bit FIFO @ 3 Hz E1 jitter attenuation @ 40 Hz @ 400 Hz @ 100 KHz @ 1 Hz @ 20 Hz @1 KHz @ 1.4 KHz @ 70 KHz 0 0 33.3 40 40 AT&T Pub. 62411 (Figure 34 on page 74) -0.5 -0.5 +19.5 +19.5 - - dB ITU-T G.736 (Figure 34 on page 74) 33 24 56 UI UI UI 6 3.5 6 17 Hz Hz Hz UI Delay through the Jitter attenuator only. Add receive and transmit path delay for total throughput delay. FIFO 32bit FIFO 3 6 Hz Hz 3.5 3 Hz Hz FIFO 32bit FIFO 3.5 2.5 Hz Hz Min Typ 2.5 Max Unit Hz Test Condition
Sinusoidal jitter modulation
T1 jitter attenuation
-
-
dB
Output Jitter in remote loopback1 1. Guaranteed by design and other correlation methods.
0.060
0.11
UI
ETSI CTR12/13 Output jitter
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QUAD T1/E1/J1 Transceiver -- LXT386
Table 42. Analog Test Port Characteristics
Parameter 3 dB bandwidth Input voltage range Output voltage range Sym At13db At1iv At2ov Min 0 0 Typ 5 Max VCC VCC Unit MHz V V Test Condition
Table 43. Transmit Timing Characteristics
Parameter E1 Master clock frequency T1 Master clock tolerance Master clock duty cycle E1 Output pulse width T1 E1 Transmit clock frequency T1 Transmit clock tolerance Transmit clock burst rate Transmit clock duty cycle E1 TPOS/TNEG pulse width (RZ mode) TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time Delay time OE Low to driver High Z Delay time TCLK Low to driver High Z Tclkt1 Tclkt Tclkb Tdc Tmpwe1 Tsut Tht Toez Ttz -50 10 236 20 20 50 1.544 - - - - 60 +50 20 90 252 1 75 MHz ppm MHz % ns ns ns Gapped transmit clock NRZ mode RZ mode (TCLK = H for >16 clock cycles) Tw Tclke1 291 324 2.048 356 ns MHz MCLK - - Tw - -100 40 219 1.544 - - 244 - 100 60 269 MHz ppm % ns Sym MCLK Min - Typ 2.048 Max - Unit MHz Test Condition
s s
Figure 18. Transmit Clock Timing Diagram
TCLK
TPOS TNEG
tSUT
tHT
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 44. Receive Timing Characteristics
Parameter E1 Clock recovery capture range T1 Receive clock duty cycle 1 Receive clock pulse width 1 E1 T1 E1 Receive clock pulse width Low time T1 E1 Receive clock pulse width High time T1 Rise/fall time
4
Sym - - Rckd Tpw Tpw Tpwl Tpwl Tpwh Tpwh Tr E1 T1 E1 Tpwdl Tpwdl Tsur T1 E1
Min - - 40 447 583 203 259 203 259 20 200 250 200 200 200
Typ 80 180 50 488 648 244 324 244 324 - 244 324 244 324 244 324 -
Max - - 60 529 713 285 389 285 389 - 300 400 - - - - 5
Unit ppm ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Condition Relative to nominal frequency MCLK = 100 ppm
@ CL=15 pF
RPOS/RNEG pulse width (MCLK=H) 2
RPOS/RNEG to RCLK rising setup time
RCLK Rising to RPOS/RNEG hold time T1 Delay time between RPOS/RNEG and RCLK
Thr 200 - - MCLK = H 3
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 2. Clock recovery is disabled in this mode. 3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit. 4. For all digital outputs.
Figure 19. Receive Clock Timing Diagram
tPW
RCLK
tPWH
tPWL
tSUR
tHR
RPOS RNEG
CLKE = 1
tSUR tHR
RPOS RNEG
CLKE = 0
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QUAD T1/E1/J1 Transceiver -- LXT386
Table 45. JTAG Timing Characteristics
Parameter Cycle time J-TMS/J-TDI to J-TCK rising edge time J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to J-TDO valid Sym Tcyc Tsut Tht Tdod Min 200 50 50 Typ Max 50 Unit ns ns ns ns Test Conditions
Figure 20. JTAG Timing
tCYC
TCK
tSUR tHT
TMS TDI
tDOD
TDO
Table 46. Intel Mode Read Timing Characteristics
Parameter2 Address setup time to latch Valid address latch pulse width Latch active to active read setup time Chip select setup time to active read Chip select hold time from inactive read Address hold time from inactive ALE Active read to data valid delay time Address setup time to RD inactive Address hold time from RD inactive Inactive read to data tri-state delay time Valid read signal pulse width Inactive read to inactive INT delay time Active chip select to RDY delay time Active ready Low time Inactive ready to tri-state delay time Sym Tsalr Tvl Tslr Tscsr Thcsr Thalr Tprd Thar Tsar Tzrd Tvrd Tint Tdrdy Tvrdy Trdyz Min 10 30 10 0 0 5 10 1 5 3 60 - 0 - - - - - - - - - - - 50 - - 35 - 10 12 40 3 Typ1 - - - - - Max - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 21. Non-Multiplexed Intel Mode Read Timing
tSAR
A4 - A0
ADDRESS tHAR
ALE
(pulled High)
tSCSR tHCSR
CS
tVRD
RD
tPRD tZRD
D7 - D0
DATA OUT tINT
INT
tDRDY tDRDY Tristate tVRDY tRDYZ Tristate
RDY
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QUAD T1/E1/J1 Transceiver -- LXT386
Figure 22. Multiplexed Intel Read Timing
tVL tSLR
ALE
tSCSR tHSCR
CS
tVRD
RD
tSALR tHALR ADDRESS
tPRD
tZRD DATA OUT tINT
AD7-AD0
INT
tDRDY tDRDY Tristate tVRDY tRDYZ Tristate
RDY
Table 47. Intel Mode Write Timing Characteristics
Parameter2 Address setup time to latch Valid address latch pulse width Latch active to active write setup time Chip select setup time to active write Chip select hold time from inactive write Address hold time from inactive ALE Data valid to write active setup time Data hold time to active write Address setup time to WR inactive Address hold time from WR inactive Sym Tsalw Tvl Tslw Tscsw Thcsw Thalw Tsdw Thdw Thaw Tsaw Min 10 30 10 0 0 5 40 30 2 6 - - - - - - - - Typ1 - - - - - Max - - - - - Unit ns ns ns ns ns ns ns ns ns ns Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. 3. These times don't apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset Operation and Host Mode sections for more information.
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LXT386 -- QUAD T1/E1/J1 Transceiver
Table 47. Intel Mode Write Timing Characteristics (Continued)
Parameter2 Valid write signal pulse width Inactive write to inactive INT delay time Chip select to RDY delay time Active ready Low time Inactive ready to tri-state delay time3
3
Sym Tvwr Tint Tdrdy Tvrdy Trdyz
Min 60 - 0 - -
Typ1 - - - - -
Max - 10 12 40 3
Unit ns ns ns ns ns
Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. 3. These times don't apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset Operation and Host Mode sections for more information.
Figure 23. Non-Multiplexed Intel Mode Write Timing
tSAW
A4-A0
ADDRESS
ALE
(pulled High)
tSCSW tHCSW
tHAW
CS
tVWR
WR
tHDW tSDW
D7-D0
WRITE DATA tINT
INT
tDRDY tDRDY Tristate tVRDY tRDYZ Tristate
RDY
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QUAD T1/E1/J1 Transceiver -- LXT386
Figure 24. Multiplexed Intel Mode Write Timing
tSLW
ALE
tVL tSCSW tHCSW
CS
tVWR
WR
tHALW tSALW tSDW WRITE DATA tINT tHDW
AD7-AD0 INT
ADDRESS
tDRDY tDRDY Tristate tVRDY tDRDYZ Tristate
RDY
Table 48. Motorola Bus Read Timing Characteristics
Parameter2 Address setup time to address or data strobe Address hold time from address or data strobe Valid address strobe pulse width R/W setup time to active data strobe R/W hold time from inactive data strobe Chip select setup time to active data strobe Chip select hold time from inactive data strobe Address strobe active to data strobe active delay Delay time from active data strobe to valid data Delay time from inactive data strobe to data High Z Valid data strobe pulse width Inactive data strobe to inactive INT delay time Data strobe inactive to address strobe inactive delay DS asserted to ACK asserted delay DS deasserted to ACK deasserted delay Active ACK to valid data delay Sym Tsar Thar Tvas Tsrw Thrw Tscs Thcs Tasds Tpds Tdz Tvds Tint Tdsas Tdackp Tdack Tpack Min 10 5 95 10 0 0 0 20 3 3 60 - 15 - - - Typ1 - - - - - - - - - - - - - - - - Max - - - - - - - - 30 30 - 10 - 40 10 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.
Datasheet
65
LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 25. Non-Multiplexed Motorola Mode Read Timing
A4-A0
ADDRESS tSAR tHAR
AS R/W
(pulled High)
tSRW tHRW
tSCS
tHCS
CS
tVDS
DS
tPDS tDZ DATA OUT tINT
D7-D0
INT
tDACKP tPACK tDACK
ACK
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 26. Multiplexed Motorola Mode Read Timing
tVAS tDSAS
AS
tSRW tHRW
R/W
tSCS tHCS
CS
tASDS tVDS
DS
tSAR tPDS tHAR ADDRESS DATA OUT tINT tDZ
D7-D0
INT
tDACKP tPACK tDACK
ACK
Table 49. Motorola Mode Write Timing Characteristics
Parameter2 Address setup time to address strobe Address hold time to address strobe Valid address strobe pulse width R/W setup time to active data strobe R/W hold time from inactive data strobe Chip select setup time to active data strobe Chip select hold time from inactive data strobe Address strobe active to data strobe active delay Data setup time to DS deassertion Data hold time from DS deassertion Valid data strobe pulse width Inactive data strobe to inactive INT delay time Sym Tsas Thas Tvas Tsrw Thrw Tscs Thcs Tasds Tsdw Thdw Tvds Tint Min 10 5 95 10 0 0 0 20 40 30 60 - Typ1 - - - - - - - - - - - - Max - - - - - - - - - - - 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.
Datasheet
67
LXT386 -- QUAD T1/E1/J1 Transceiver
Table 49. Motorola Mode Write Timing Characteristics (Continued)
Parameter2 Data strobe inactive to address strobe inactive delay Active data strobe to ACK output enable time DS asserted to ACK asserted delay Sym Tdsas Tdack Tdackp Min 15 0 Typ1 - - - Max - 12 40 Unit ns ns ns Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF.
Figure 27. Non-Multiplexed Motorola Mode Write Timing
A4-A0
ADDRESS tSAS tHAS
AS (pulled High)
tSRW tHRW
R/W
tSCS tHCS
CS
tVDS
DS
tSDW tHDW
D7-D0
WRITE DATA
tINT
INT
tDACKP tDACK
ACK
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
g
Figure 28. Multiplexed Motorola Mode Write Timin
tVAS tDSAS
AS
tSRW tHRW
R/W
tSCS tHCS
CS
tASDS tVDS
DS
tSAS tHAS tHDW tSDW WRITE DATA tINT
D7-D0
ADDRESS
INT
tDACKP tDACK
ACK
Table 50. Serial I/O Timing Characteristics
Parameter Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time SCLK Low time SCLK High time SCLK rise and fall time CS falling edge to SCLK rising edge Last SCLK edge to CS rising edge CS inactive time SCLK to SDO valid delay time SCLK falling edge or CS rising edge to SDO High Z Sym Trf Tdc Tcdh Tcl Tch Tr, Tf Tcc Tcch Tcwh Tcdv Tcdz Min 5 5 25 25 10 10 50 Typ1 10 Max 100 50 5 Unit ns ns ns ns ns ns ns ns ns ns ns Test Condition Load 1.6mA, 50 pF
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
69
LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 29. Serial Input Timing
CS tCC tCH tCL SCLK tCDH
LSB CONTROL BYTE DATA BYTE
tCWH tCCH
tDC SDI
LSB
tCDH
MSB
Figure 30. Serial Output Timing
CLKE = 0 1 SCLK CS SDO CLKE = 1 1 SCLK CS SDO 0 1 2 3 4 5 tCDZ 6 tCCH 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tCDZ 0 1 2 3 4 5 6 7 tCCH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Table 51. Transformer Specifications3
Tx/Rx Turns Ratio1 Primary Inductance mH (min.) 1.2 1.2 Leakage Inductance H (max.) 0.60 0.60 Interwinding Capacitance pF (max.) 60 60 DCR (max.) 0.70 pri 1.20 sec 1.10 pri 1.10 sec Dielectric Breakdown Voltage V2 (min.) 1500 Vrms 1500 Vrms
TX RX
1:2 1:2
1. Transformer turns ratio accuracy is 2%. 1. This parameter is application dependent.LIU side: Line side. 2. Refer to the FAQ or Application Note 118 for recommended magnetics.
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Table 52. G.703 2.048 Mbit/s Pulse Mask Specifications
Cable Parameter TWP Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse amplitudes at nominal half amplitude 120 3.0 0 0.30 244 95-105 95-105 Coax 75 2.37 0 0.237 244 95-105 95-105 Unit
V V ns % %
Figure 31. E1, G.703 Mask Templates
269 ns (244+25) 20%
V = 100%
10% 10%
20%
194 ns (244- 50)
NOMINAL PULSE 50%
244 ns 219 ns (244-25) 10% 10% 10% 10%
0%
20%
488 ns (244+244)
Table 53. T1.102 1.544 Mbit/s Pulse Mask Specifications
Cable Parameter TWP Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes 100 3.0 0 0.15 324 95-105 Unit
V V ns %
Datasheet
71
LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 32. T1, T1.102 Mask Templates
1.20 1.00 0.80 0.60 0.40 0.20 0.00 0.00 -0.20 -0.40 -0.60 Tim e [UI]
Normalized Amplitude -0.80
-0.60
-0.40
-0.20
0.20
0.40
0.60
0.80
1.00
1.20
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 33. LXT386 Jitter Tolerance Performance
1000 UI
100 UI
28 UI @ 4.9 Hz AT&T 62411, Dec 1990 (T1) 18 UI @ 1.8 Hz 28 UI @ 300 Hz
Jitter
LXT386 typ.
10 UI
GR-499-CORE, Dec 1995 (T1) 5 UI @ 500 Hz ITU G.823, Mar 1993 (E1) 0.4 UI @ 10 kHz
1 UI
1.5 UI @ 20 Hz 1.5 UI @ 2.4 kHz 0.2 UI @ 18 kHz
.1 UI 1 Hz
0.1 UI @ 8 kHz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
Datasheet
73
LXT386 -- QUAD T1/E1/J1 Transceiver
Figure 34. Jitter Transfer Performance
E1
10 dB ITU G.736 Template
0.5 dB @ 3Hz 0.5 dB @ 40Hz
0 dB
-10 dB
f 3dB =2.5 Hz
Gain
-20 dB
-19.5 dB @ 20 kHz f 3dB =3.5 Hz -19.5 dB @ 400 Hz
-30 dB
-40 dB LXT386 typ. -60 dB
-80 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
Frequency
T1
10 dB
0 dB @ 1 Hz 0 dB @ 20 Hz 0.1 dB @ 40 Hz 0.5 dB @ 350 Hz
0 dB
AT&T Pub 62411 GR-253-CORE TR-TSY-000009
-10 dB
Gain
-20 dB
-6 dB @ 2 Hz -33.3 dB @ 1 kHz
-30 dB
f
3dB
= 3 Hz = 6 Hz
-33.7 dB @ 2.5kHz -40 dB @ 1.4 kHz
f
3dB
-40 dB @ 70 kHz
-40 dB LXT386 typ. -60 dB
-60 dB @ 57 Hz
-49.2 dB @ 15kHz
-80 dB 1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 35. Output Jitter for CTR12/13 applications
0.2
Jitter Amplitude (Ulpp)
0.15
0.1
LXT386 typ, f 3dB = 2.5Hz & 3.5 Hz
0.05
0 10 Hz 20 Hz 100 Hz 1 kHz Frequency 10 kHz 100 kHz
6.1
Recommendations and Specifications
AT&T Pub 62411 ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 -1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria Bellcore GR-499-CORE Transport Systems Generic Requirements G.703 Physical/electrical characteristics of hierarchical digital interfaces G. 704 Functional characteristics of interfaces associated with network nodes G.735 Characteristics of Primary PCM multiplex equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s G.772 Protected Monitoring Points provided on Digital Transmission Systems G.775 Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/ s hierarchy O.151 Specification of instruments to measure error performance in digital systems OFTEL OTR-001 Short Circuit Current Requirements ETS 300166 Physical and Electrical Characteristics ETS 300386-1 Electromagnetic Compatibility Requirement
Datasheet
75
LXT386 -- QUAD T1/E1/J1 Transceiver
7.0
Mechanical Specifications
Figure 36. 60 Plastic Ball Grid Array (PBGA) Package Dimensions
160 PBGA Package * Part Number LXT386BE * Extended Temperature Range (-40C to 85 C)
15.00 13.00 0.20 4.72 0.10 PIN #A1 CORNER 1.00 1.00 REF 13.00
A
0.50 B 0.10 C
PIN #A1 ID 4.72 0.10
D E F
13.00 15.00 0.20 1.00
G H J K L M N P
13.0
O1.00 (3 plcs)
14 13 12 11 10 9
8
76
54
3
21
1.00 R
TOP VIEW
BOTTOM VIEW
0.85
1.61 0.19
NOTE:
1. ALL DIMENSIONS IN MILLIMETERS. 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994. 3. TOLERANCE = 0.05 UNLESS SPECIFIED OTHERWISE.
SEATING PLANE
0.36 0.04
0.40 0.10
SIDE VIEW
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Datasheet
QUAD T1/E1/J1 Transceiver -- LXT386
Figure 37. 100 Pin Low Quad Flat Packages (LQFP) Dimensions
100 Pin LQFP * Part Number LXT386LE * Extended Temperature Range (-40C to 85 C)
ALL DIMENSIONS IN MILLIMETERS
All dimensions and tolerances conform to ANSI Y14.5M-1982.
16.00 BSC 14.00 BSC 12.00 BSC
16.00 BSC
14.00 BSC
12.00 BSC
0.22 0.05
Pin #1 Index
0.50 BSC
123
See Detail "A"
1.40 0.05
1.60 max
0.05 min 0.15 max
DETAIL "A"
0.60 0.15 1.00 REF
0.20 min
Datasheet
77

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